--This code is for a 4x8 multiplier

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Full adder taken from http://xup.msu.edu/howtos/add/
entity add_1_bit is
    port (
      x: in std_logic;
      y: in std_logic;
      cin: in std_logic;
      sum: out std_logic;
      cout: out std_logic
    );
end add_1_bit;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA_PLUS is
	port(FAP_Ain : in std_logic;
		  FAP_Bin : in std_logic;
		  FAP_OnOff : in std_logic;
		  FAP_AddSub : in std_logic;
		  FAP_cin : in std_logic;
	     FAP_sum: out std_logic;
   	  FAP_cout: out std_logic
	);
end FA_PLUS;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EightbitAdder is
    Port ( Ain : in std_logic_vector(7 downto 0);
           Bin : in std_logic_vector(7 downto 0);
           total : out std_logic_vector(7 downto 0);
           OnOff : in std_logic;
           AddSub : in std_logic;
			  carryout : out std_logic);
end EightbitAdder;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fourBYeight is
	port (eightIn : in std_logic_vector (7 downto 0);
			fourIn : in std_logic_vector (3 downto 0);
			eightOut : out std_logic_vector (7 downto 0);
			multCarry : out std_logic
			);
end;

--Full adder taken from http://xup.msu.edu/howtos/add/
architecture rtl of add_1_bit is
begin
    sum <= x xor y xor cin;
    cout <= (x and y) or (x and cin) or (y and cin);
end rtl;

architecture FullAdderPlus of FA_PLUS is
component MY_XOR
	port(orX, orY : in std_logic; orOut : out std_logic);
end component;
component MY_AND
	port(andX, andY : in std_logic; andOut : out std_logic);
	end component;
component add_1_bit
    port (
      x: in std_logic;
      y: in std_logic;
      cin: in std_logic;
      sum: out std_logic;
      cout: out std_logic
    );
end component;
signal signal1, signal2 : std_logic;
begin
theAND : MY_AND port map(andX => FAP_Ain, andY => FAP_OnOff, andOut => signal1);
theOR : MY_XOR port map(orX => FAP_Bin, orY => FAP_AddSub, orOut => signal2);
bit1 : add_1_bit port map(x => signal1, y => signal2, cin => FAP_cin, sum => FAP_sum, cout => FAP_cout);
end FullAdderPlus;


architecture eight_bit of EightbitAdder is
component FA_PLUS
	port(FAP_Ain : in std_logic;
		  FAP_Bin : in std_logic;
		  FAP_OnOff : in std_logic;
		  FAP_AddSub : in std_logic;
		  FAP_cin : in std_logic;
	     FAP_sum: out std_logic;
   	  FAP_cout: out std_logic
	);
end component;
signal carry1, carry2, carry3, carry4, carry5, carry6, carry7 : std_logic;
begin
bit1 : FA_PLUS port map(FAP_Ain => Ain(0), FAP_Bin => Bin(0), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => AddSub, FAP_sum => total(0), FAP_cout => carry1);
bit2 : FA_PLUS port map(FAP_Ain => Ain(1), FAP_Bin => Bin(1), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry1, FAP_sum => total(1), FAP_cout => carry2);
bit3 : FA_PLUS port map(FAP_Ain => Ain(2), FAP_Bin => Bin(2), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry2, FAP_sum => total(2), FAP_cout => carry3);
bit4 : FA_PLUS port map(FAP_Ain => Ain(3), FAP_Bin => Bin(3), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry3, FAP_sum => total(3), FAP_cout => carry4);
bit5 : FA_PLUS port map(FAP_Ain => Ain(4), FAP_Bin => Bin(4), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry4, FAP_sum => total(4), FAP_cout => carry5);
bit6 : FA_PLUS port map(FAP_Ain => Ain(5), FAP_Bin => Bin(5), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry5, FAP_sum => total(5), FAP_cout => carry6);
bit7 : FA_PLUS port map(FAP_Ain => Ain(6), FAP_Bin => Bin(6), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry6, FAP_sum => total(6), FAP_cout => carry7);
bit8 : FA_PLUS port map(FAP_Ain => Ain(7), FAP_Bin => Bin(7), FAP_OnOff => OnOff, FAP_AddSub => AddSub, FAP_cin => carry7, FAP_sum => total(7), FAP_cout => carryout);
end eight_bit;

architecture multiplier of fourBYeight is
component EightBitAdder
    Port ( Ain : in std_logic_vector(7 downto 0);
           Bin : in std_logic_vector(7 downto 0);
           total : out std_logic_vector(7 downto 0);
           OnOff : in std_logic;
           AddSub : in std_logic;
			  carryout : out std_logic);
end component;
signal zeroIn, carry1, carry2, carry3 : std_logic;
signal add1, add2, add3: std_logic_vector (7 downto 0);
begin
--Make the A input the eight bit number to be multiplied
adder1 : EightBitAdder port map(Ain(7 downto 0) => eightIn(7 downto 0),
--Nothing to carry in.
	Bin(7) => zeroIn, Bin(6) => zeroIn, Bin(5) => zeroIn, Bin(4) => zeroIn, 
	Bin(3) => zeroIn, Bin(2) => zeroIn, Bin(1) => zeroIn, Bin(0) => zeroIn, 
--Multiply the first part of the four bit input number
	OnOff => fourIn(0), AddSub => zeroIn,
--push answer onto signal
	total(7 downto 0) => add1(7 downto 0), carryout => carry1);

--Make the A input the eight bit number to be multiplied
adder2 : EightBitAdder port map(Ain(7 downto 0) => eightIn(7 downto 0),
--take the top 6 from the last add and make it the bottom 6 and then tack on the carry
	Bin(7) => carry1, Bin(6 downto 0) => add1(7 downto 1),
--Multiply the next part of the input number
    	OnOff => fourIn(1), AddSub => zeroIn,
--push answer onto signal
	total(7 downto 0) => add2(7 downto 0), carryout => carry2);

--Make the A input the eight bit number to be multiplied
adder3 : EightBitAdder port map(Ain(7 downto 0) => eightIn(7 downto 0),
--take the top 6 from the last add and make it the bottom 6 and then tack on the carry
	Bin(7) => carry2, Bin(6 downto 0) => add2(7 downto 1),
--Multiply the next part of the input number
     	OnOff => fourIn(2), AddSub => zeroIn,
--push answer onto signal
	total(7 downto 0) => add3(7 downto 0), carryout => carry3);

--Make the A input the eight bit number to be multiplied
adder4 : EightBitAdder port map(Ain(7 downto 0) => eightIn(7 downto 0),
--take the top 6 from the last add and make it the bottom 6 and then tack on the carry
	Bin(7) => carry3, Bin(6 downto 0) => add3(7 downto 1), 
--Multiply the next part of the input number
	OnOff => fourIn(3), AddSub => zeroIn,
--push answer onto total.  Rightmost 3 bits from other multiplies are dropped
	total(7 downto 0) => eightOut(7 downto 0), carryout => multCarry);

end multiplier;